1. Field of the Invention
The present invention relates generally to semiconductor manufacturing, and more particularly to a method of forming self-aligned contacts in a semiconductor device.
2. Description of the Related Art
The integration of integrated circuit devices continues to increase. As a result, pattern sizes are continuing to get smaller. Further, the wavelength of the light source used in the exposure process is also getting shorter. As an example, wavelengths have decreased from g-line (wave length of 436 nm) and i-line (wave length of 365 nm) to KrF eximer laser (wave length of 248 nm). However, the degree of photolithographic resolution has not kept pace with the degree of integration of integrated circuit devices. One illustration of this occurs in the cell array region of DRAM devices where strict design rules are required and a slight misalignment is not acceptable. Because the degree of photolithographic resolution is not high enough, a self-aligned contact process has been adopted.
However, there are some problems with the self-aligned contact process. Due to the limited photolithographic resolution, it is difficult to form a bit line contact and a storage node contact on the same plan-face through the self-aligned contact process. Desired contact patterns cannot be obtained because the distance between adjacent patterns is too small. The result is that adjacent contacts are undesirably joined together.
To overcome the above mentioned problem, a method has been disclosed which forms an enlarged contact pattern that merges a bit line contact and a storage node contact and uses a photoresist pattern and a gate line as an etching mask. For example, Y. Kohyama et al. disclosed a method of forming self-aligned contacts entitled xe2x80x9cA Fully Printable Self-Aligned and Planarized Stacked Capacitor DRAM Cell Technology for 1 GBit DRAM and Beyond.xe2x80x9d
FIG. 1 and FIGS. 2A-2B show schematically a plan view and cross-sectional views, respectively, to explain the self-aligned contacts technology of the above cited reference. Referring to FIG. 1, bar shaped active regions 11 are defined on a semiconductor substrate (not shown). Gate lines 15 intersect the bar shaped active regions 11. Interlayer dielectric layer 18 is composed of an oxide layer and covers the gate lines 15. A self-aligned contact mask 20 (i.e., a photoresist pattern) is formed on the interlayer dielectric layer 18. The self-aligned contact mask 20 has the same basic pattern as the active regions 11, but is shifted by a half pitch to the gate direction. Thus, in FIG. 1 the regions forming the contact mask 20 appear just to the left of the active regions 11.
Referring to FIG. 2A, a device isolation region 10 is formed on a semiconductor substrate (not shown). A plurality of gate lines 15 is formed on the semiconductor substrate including the device isolation region 10. The gate lines 15 are composed of a polysilicon layer 12 and a WSi polycide layer 13 with a SiN hard mask 14 and SiN sidewall spacers 16. Interlayer dielectric layer 18 is deposited on the resulting structure and planarized by a CMP process. The self-aligned contact mask 20 is formed on the interlayer dielectric layer 18.
Referring to FIGS. 2A and 2B, using the self-aligned contact mask 20, the interlayer dielectric layer 18 is etched to form a plurality of self-aligned contact openings 22. If the oxide 18 etching selectivity with respect to silicon nitride hard mask 14 and spacer 16 is poor, then silicon nitride layers 14 and 16 may undesirably be etched resulting a reduced shoulder margin (shortest distance between the gate electrode metal and an adjacent conductive plug subsequently formed in the contact opening 22 adjacent to the gate spacer 16) at the upper edges of the exposed regions of the SiN hard mask 14. It is undesirable if those portions of the SiN mask 14 and the SiN sidewall spacers 16 which cover the upper edges of the gate electrodes 12 and 13 become thin resulting a small shoulder margin (see reference number 23). This leads to a leakage current flow between the conductive plug (filling material), which is subsequently formed in the contact openings 22, and the gate electrode layers 12 and 13. In order to minimize the leakage current between the gate electrode and the contact plug, it is required to prevent thinning of the nitride hard mask (14) and sidewall spacers (16) in the exposed regions during etching of interlayer insulator layer 18.
To overcome this problem, the silicon nitride hard mask 14 can be formed with a greater thickness. Such increased thickness, however, makes it difficult to deposit the subsequent interlayer dielectric layer 18 due to the resulting high aspect ratio of the gate electrode configuration. Voids may then, undesirably, be formed in the interlayer dielectric layer 18 and such voids may occur between adjacent cells.
The present invention is directed to overcoming or at least reducing the effects of one or more of the problems set forth above.
A feature of an embodiment of the present invention is directed toward providing a method of forming self-aligned contacts which can prevent a silicon nitride layer from being etched during a self-aligned contact etching process.
In one embodiment, in order to protect the silicon nitride hard mask and spacer, a polysilicon layer is deposited thereon. Polysilicon has better etching selectivity, with respect to a later-formed oxide layer, than the silicon nitride layer. Accordingly, the silicon nitride layer is not etched during the self-aligned contact etching. Current leakage between gate electrodes and later-formed self-aligned contact pads is thereby suppressed. Moreover, the polysilicon layer may be formed as a thin layer because of its good etching selectivity with respect to the oxide layer. Therefore, the thickness of the silicon nitride hard mask may be reduced, thereby reducing the height of the gate electrode configuration. To achieve this and other advantages and in accordance with a feature of the present invention, a device isolation region is formed on a semiconductor substrate. A gate oxide layer is formed on the resulting structure to insulate a later-formed gate electrode configuration from the semiconductor substrate. A gate electrode layer, a first gate mask layer, and a second gate mask layer are sequentially stacked on the gate oxide layer. Using a patterned photoresist layer, selected portions of the stacked layers are etched to form a plurality of gate electrode configurations. Sidewall spacers are formed on both sidewalls of each gate electrode configuration.
An insulating layer composed of an oxide layer is deposited to cover the spaced-apart gate electrode configurations. Using a self-aligned mask pattern, selected portions of the insulating layer are etched to form self-aligned contact openings that expose portions of the semiconductor substrate between the gate electrode configurations. During this self-aligned etching, the second mask layer protects the underlying first mask layer. The resulting contact openings are filled with conductive material such as doped polysilicon and planarized to form self-aligned contact pads.
More specifically, in this embodiment the gate electrode layer is made of a stack including a polysilicon layer and a metal silicide layer, such as a tungsten silicide layer, and each layer has a thickness of about 1,000 xc3x85. The first mask layer is made of a silicon nitride layer and has a thickness in a range from about 500 xc3x85 to about 1,000 xc3x85. The second mask layer is made of a material that has a better etching selectivity, with respect to an insulating layer (an oxide layer), than the silicon nitride layer, in order to protect the silicon nitride layer. As an example, the second mask layer may be formed of polysilicon. A polysilicon layer is formed as a thin layer due to its good etching selectivity. Accordingly, the silicon nitride layer can be formed as a thin layer, as noted above, as compared with a conventional method wherein a nitride layer is formed to a thickness of at least 1,500 xc3x85. Sidewall spacers are made of a silicon nitride layer and have a thickness of about 500 xc3x85.
Deposition of the oxide insulating layer utilizes an HDP (high density plasma) deposition apparatus. The HDP deposition apparatus has the advantage of depositing a desired layer while also etching it. Accordingly, the resulting oxide layer has good filling characteristics without any void formation therein.
Alternatively, a third mask layer further formed on the second mask layer. The third mask layer may be formed of a HTO (high temperature oxide) layer. This HTO layer has a good etching selectivity with respect to a tungsten silicide layer. In this case, the formation of the gate electrode configurations is as follows. Using the photoresist layer patterned for a gate electrode, the third mask layer, second mask layer, and first mask layer are etched. Using this patterned HTO layer as a mask, the tungsten silicide layer and the polysilicon layer are etched to form the gate electrode configurations.
In order to protect the semiconductor substrate during self-aligned contact etching, a silicon nitride layer may be formed to a thickness of about 100 xc3x85 before deposition of the oxide insulating layer.
In accordance with one aspect of the invention, there is provided a method of forming self-aligned contacts in a semiconductor device. The method includes forming a gate oxide layer, a gate electrode layer, a first gate mask, and a second gate mask on a semiconductor substrate. The method further includes etching the second gate mask, the first gate mask, and the gate electrode layer to form gate electrode configurations which are spaced apart. The method further includes forming gate spacers on sidewalls of each of the spaced apart gate electrode configurations and forming an interlayer insulating layer on an entire surface of the semiconductor substrate. The method further includes using a self-aligned contact mask and etching the interlayer insulating layer to expose the semiconductor substrate. The first gate mask, the second gate mask, and the gate spacers each have an etch selectivity with respect to the interlayer insulating layer. The second gate mask has a better etch selectivity, with respect to the interlayer insulating layer, than the first gate mask.
In accordance with another aspect of the invention, there is provided another method of forming self-aligned contacts in a semiconductor device. The method includes forming gate electrode configurations which are spaced apart. Each gate electrode configuration includes a gate electrode layer, a first gate mask, and a second gate mask on a semiconductor substrate. The method further includes forming gate spacers on sidewalls of each of the spaced apart gate electrode configurations and forming an interlayer insulating layer on the gate electrode configurations and the intervening spaces. The first gate mask, the second gate mask, and the gate spacers each have an etch selectivity with respect to the interlayer insulating layer. The second gate mask has a better etch selectivity, with respect to the interlayer insulating layer, than the first gate mask. The method further includes using a self-aligned contact mask and etching the interlayer insulating layer to expose the semiconductor substrate.
In accordance with another aspect of the invention, there is provided yet another method of forming self-aligned contacts in a semiconductor device. The method includes forming a gate oxide layer, a gate electrode layer, a first gate mask, a second gate mask, and a third gate mask on a semiconductor substrate. The third gate mask has etching selectivity with respect to the gate electrode layer. The method further includes etching the third gate mask, the second gate mask, and the first gate mask. The method further includes etching the gate electrode layer, using the third gate mask as an etching mask, thus forming gate electrode configurations which are spaced apart. The method further includes forming gate spacers on sidewalls of each of the spaced apart gate electrode configurations. The third gate mask is removed during the forming of the gate spacers. The method further includes forming a thin material layer to protect the semiconductor substrate, and forming an interlayer insulating layer on an entire surface of the semiconductor substrate. The first gate mask, the second gate mask, and the gate spacers each have an etch selectivity with respect to the interlayer insulating layer. The second gate mask has a better etch selectivity, with respect to the interlayer insulating layer, than the first gate mask. The method further includes using a self-aligned contact mask and etching the interlayer insulating layer to expose the semiconductor substrate. The method further includes removing the self-aligned contact mask, filling the exposed semiconductor substrates with a conductive material, and planarizing the conductive material and the second gate mask and stopping at the first gate mask.
In accordance with another aspect of the invention, there is provided a semiconductor device. The semiconductor device includes a device isolation region, gate electrodes, an interlayer insulating layer, and a self-aligned contact pattern. The gate electrodes are on the device isolation region. Each gate electrode includes a gate electrode layer, a first gate mask layer on the gate electrode layer, a second gate mask layer on the first gate mask layer, and gate spacers on each side of each gate electrode. The gate spacers cover the sides of the gate electrode layer, the first gate mask, and the second gate mask. The interlayer insulating layer is formed on the gate electrodes and in the spaces between the gate electrodes. The first gate mask layer, the second gate mask layer, and the gate spacers each have an etch selectivity with respect to the interlayer insulating layer. The second gate mask layer has a better etch selectivity, with respect to the interlayer insulating layer, than the first gate mask layer. The self-aligned contact pattern is formed on the interlayer insulating layer and at least one of the gate electrodes. The self-aligned contact pattern and the second gate mask layer of one of the gate electrodes can be used as an etching mask to etch the interlayer insulating layer.
In accordance with another aspect of the invention, the exposed upper shoulder regions of the SiN first gate mask layer remained flat even after etching the interlayer dielectric layer when a second gate mask layer, that has a better etch selectivity with respect to the interlayer dielectric layer than the first gate mask layer , is used. On the other hand, etching of the interlayer dielectric layer without using the second gate mask layer on the SiN gate mask layer results in a pyramid shape formation at the exposed upper shoulder regions of the SiN gate mask and the SiN sidewall spacer structure. The improved shoulder margin (shortest distance between the gate electrode metal and an adjacent conductive plug subsequently formed in the contact opening adjacent to the gate spacer) due to the use of the second gate mask layer helps to minimize the leakage current flow between the gate electrode and the conductive plug formed subsequently in the contact opening.